Current communication circuits have a high level of integration and achieve high performance by minimizing parasitic effects. During both product characterization and normal product usage, it is often desired to observe signal waveforms on critical high-speed internal nodes. However, current integrated circuits cannot be directly probed internally without significantly altering the signal to be observed.
Internal characterization is a very important, time-consuming and expensive part of the complete design cycle. At the current design speeds, sampling the signal internally is very difficult and requires dedicated output pads with linear buffers. These elements require significant area and their design is difficult. Even if turned off in normal operation, their presence can cause detrimental effects that limit the bandwidth and require improved performance from the circuits ahead. The cost of high-speed test equipment is also substantial.
Most existing methods for indirectly probing internal nodes use dedicated circuits to apply time and voltage offsets to probe different parts of the waveform. FIG. 1 shows a typical prior art signal waveform analysis system. A transmitter 20 sends digital information to a receiver 22 through a transmission channel 24. The intent is to evaluate the waveform of the recovered signal 26. The signal 26 is sampled by a sampler 28 with a timing reference 30, derived from the incoming signal 26 through a clock recovery circuit 32, and further adjusted by a clock skew circuit 34. The voltage threshold 36 of the sampler 24 is controlled by a threshold control circuit 38. The output 40 of the sampler 28 is a digital signal that is compared with the expected pattern at a comparator 42. The number of discrepancies, or bit errors, is recorded in an error counter 44 for the duration of the test. The measurement is repeated with different combinations of clock skews, generated by clock skew circuit 34, and threshold values, generated by threshold control circuit 38. The representation of the number of errors as a function of both the clock skew and the threshold maps a 2-D representation of the signal during a clock cycle. This map represents the probability of bit errors as a function of clock skew and sampler threshold during the bit period.
A common way to represent a communication signal waveform is to plot its amplitude vs. the time elapsed from a fixed instant relative to the current bit period start. The graph resulting from showing many such waveforms collected over different bit periods is called an eye diagram. The bit error map described above has a shape similar to that of the eye diagram, as its probability distribution matches that of the signal traces around the “center opening” of the eye diagram.
Such previously known signal waveform analysis systems typically require a known pattern to be transmitted, in order to be able to compare the recovered signal with the expected value. This limits the application to systems where the transmitter is fully controllable, and can send one of the patterns that can be detected at the output. In a practical application, the data transmitted can be difficult to control and programming this configuration can require lengthy setup procedures. The analysis of critical internal node signal waveforms is also helpful to identify problems that arise when a specific pattern is transmitted. However, if the specific pattern is not one of the pre-defined test patterns, previously known analysis systems are not useful for this purpose.